Mentor Graphics Design-for-Test Tools Chosen by Faraday

WILSONVILLE, Ore.--(BUSINESS WIRE)--July 8, 2002--Mentor Graphics Corporation (Nasdaq:MENT - News) today announced that Faraday Technology Corporation has selected Mentor Graphics® Design-for-Test (DFT) tools for its system-on-chip (SoC) design flows.

Faraday selected Mentor Graphics for its proven DFT technology and ability to improve productivity and test quality and reduce test cost.

As a leading supplier of silicon-proven intellectual property and a leading provider of SoC design services, Faraday recognizes today's SoC designs require multiple test solutions to guarantee thorough testing of these devices. Mentor Graphics offers the industry's most complete portfolio of DFT tools for testing complex SoC designs. These tools provide high fault coverage as well as the flexibility to fit into any design flow. Faraday will use the FastScan(TM) tool for automatic test pattern generation (ATPG) and the MBISTArchitect(TM) tool for memory built-in self-test (BIST). To complete its test flow, Faraday also adopted the BSDArchitect(TM) tool for automated boundary scan implementation, the DFTAdvisor(TM) tool for scan synthesis and testability analysis and the DFTInsight(TM) tool for graphical DFT debug and analysis.

"We work on very aggressive development schedules with limited bandwidth," said Dr. George Huang, vice president of ASIC Technology for Faraday Technology. "Mentor Graphics offers the DFT products we need to generate very high quality tests for our SoC designs in the least amount of time."

Faraday was impressed with the MBISTArchitect tool's comprehensive array of memory BIST features designed to save chip area and achieve high fault coverage with minimal test time. Faraday can select from a set of pre-defined industry-standard algorithms, such as March C and checkerboard, or the tool's own MBIST Flex(TM) user-definable algorithm which applies at-speed tests with flexible pattern applications to detect technology specific defects. The MBIST Full-Speed(TM) feature, an at-speed BIST capability with pipelining techniques, significantly reduces test application times while the tool's comprehensive configurations facilitate high test set reusability.

FastScan provides Faraday with leading ATPG technology, an intuitive interface and a range of fault models. The tool also offers advanced fault analysis techniques, comprehensive design rule checking, pattern compression and optimization capabilities, industry-proven at-speed test generation functionality and delivery of the highest coverage test sets for their ASIC and SoC designs.

"The breadth of Mentor DFT solutions offer customers such as Faraday a comprehensive test solution for today's most complex SoC devices," said Robert Hum, vice president and general manager, Model Technology group and Design-for-Test group, Mentor Graphics. "Our leadership in the DFT industry ensures that as technologies evolve, Mentor will be ready with solutions that continue to improve test quality and reduce test costs."

About Mentor Graphics Design-for-Test Tools

Mentor Graphics provides the industry's broadest portfolio of DFT solutions for today's SoC and deep submicron designs and includes solutions for memory BIST, logic BIST, boundary scan, ATPG and embedded deterministic test (EDT(TM)). Mentor Graphics DFT Centers of Excellence are located worldwide and employ the industry's leading professionals in the research and application of proven DFT solutions. For more information visit www.mentor.com/dft.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT - News) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

About Faraday Technology Corporation

Faraday Technology Corporation has been providing remarkable ASIC design services and valuable IPs (Intellectual Properties) for customers ranging from small start-ups to large multinational IC design houses and system houses. With more than 380 employees and annual revenue of 70 million in 2001, Faraday is the largest organization of its type in the Asia-Pacific area. Headquartered in Hsinchu, Taiwan, Faraday has branch offices around the world, including the U.S.A., Japan and Europe. More information on Faraday is available at http://www.faraday.com.tw.

Mentor Graphics is a registered trademark and BSDArchitect, DFTAdvisor, DFTInsight, EDT, FastScan, MBIST Full-Speed, MBISTArchitect and MBIST Flex are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

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     Leanne White, 503/685-1984
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